33 research outputs found

    The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs

    Full text link
    The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-642-38789-0_7Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wear-out, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied.This work has been funded by Spanish Ministry of Economy ARENES project (TIN2012-38308-C02-01)Espinosa García, J.; Andrés Martínez, DD.; Ruiz, JC.; Gil, P. (2013). The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. En Dependable Computing. Springer. 76-87. https://doi.org/10.1007/978-3-642-38789-0_7S7687Narayanan, V., Xie, Y.: Reliability concerns in embedded systems design. IEEE Computer 1(39), 118–120 (2006)Hannius, O., Karlsson, J.: Impact of soft errors in a jet engine controller. In: Ortmeier, F., Daniel, P. (eds.) SAFECOMP 2012. LNCS, vol. 7612, pp. 223–234. Springer, Heidelberg (2012)Borkar, S.: Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6), 10–16 (2005)JEDEC: Measurement and reporting of alpha particle and terrestrial cosmic ray-induced soft errors in semiconductor devices. JEDEC Standard JESD89A. JEDEC (2006)Gracia-Moran, J., Gil-Tomas, D., Saiz-Adalid, L.J., Baraza, J.C., Gil-Vicente, P.J.: Experimental validation of a fault tolerant microcomputer system against intermittent faults. In: DSN, pp. 413–418 (2010)Constantinescu, C.: Intermittent faults and effects on reliability of integrated circuits. In: Proceedings of the 2008 Annual Reliability and Maintainability Symposium, pp. 370–374. IEEE Computer Society, Washington, DC (2008)Avizienis, A., Laprie, J.C., Randell, B., Landwehr, C.: Basic concepts and taxonomy of dependable and secure computing. IEEE Trans. Dependable Secur. Comput. 1, 11–33 (2004)Johnson, C., Holloway, C.: The dangers of failure masking in fault-tolerant software: Aspects of a recent in-flight upset event. In: 2007 2nd Institution of Engineering and Technology International Conference on System Safety, pp. 60–65 (October 2007)Bolchini, C., Salice, F., Sciuto, D.: Fault analysis for networks with concurrent error detection. IEEE Des. Test 15(4), 66–74 (1998)Goessel, M., Ocheretny, V., Sogomonyan, E., Marienfeld, D.: New Methods of Concurrent Checking (Frontiers in Electronic Testing), 1st edn. Springer Publishing Company, Incorporated (2008)Iyer, R.K., Rossetti, D.J.: A statistical load dependency model for cpu errors at slac. In: Twenty-Fifth International Symposium on Fault-Tolerant Computing, ‘Highlights from Twenty-Five Years’, p. 373 (June 1995)Dodd, P.E., Shaneyfelt, M.R., Felix, J.A., Schwank, J.R.: Production and propagation of single-event transients in high-speed digital logic ics. IEEE Transactions on Nuclear Science 51, 3278–3284 (2004)Nightingale, E.B., Douceur, J.R., Orgovan, V.: Cycles, cells and platters: an empirical analysisof hardware failures on a million consumer pcs. In: Proceedings of the Sixth Conference on Computer Systems, EuroSys 2011, pp. 343–356. ACM, New York (2011)Kimseng, K., Hoit, M., Tiwari, N., Pecht, M.: Physics-of-failure assessment of a cruise control module. Microelectronics Reliability 39(10), 1423–1444 (1999)Savir, J.: Detection of single intermittent faults in sequential circuits. IEEE Trans. Comput. 29(7), 673–678 (1980)Correcher, A., Garcia, E., Morant, F., Quiles, E., Rodriguez, L.: Intermittent failure dynamics characterization. IEEE Transactions on Reliability 61(3), 649–658 (2012)Sorensen, B., Kelly, G., Sajecki, A., Sorensen, P.: An analyzer for detecting intermittent faults in electronic devices. In: AUTOTESTCON 1994. IEEE Systems Readiness Technology Conference. ‘Cost Effective Support Into the Next Century’, Conference Proceedings, pp. 417–421 (September 1994)Sosnowski, J.: Transient fault tolerance in digital systems. IEEE Micro 14(1), 24–35 (1994)Bondavalli, A., Chiaradonna, S., Di Giandomenico, F., Grandoni, F.: Threshold-based mechanisms to discriminate transient from intermittent faults. IEEE Trans. Comput. 49(3), 230–245 (2000)Rashid, L., Pattabiraman, K., Gopalakrishnan, S.: Intermittent hardware errors and recovery: modelling and evaluation. In: International Conference on Quantitative Evaluation of Systems, QEST (2012)Touba, N.A., McCluskey, E.J.: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. CAD 16(7), 783–789 (1997)Nicolaidis, M., Manich, S., Figueras, J.: Achieving fault secureness in parity prediction arithmetic operators: General conditions and implementations. In: Proceedings of the 1996 European conference on Design and Test, EDTC 1996, pp. 186–193. IEEE Computer Society, Washington, DC (1996)Ko, S.B., Lo, J.C.: Efficient realization of parity prediction functions in fpgas. J. Electron. Test. 20(5), 489–499 (2004)D’Angelo, S., Sechi, G.R., Metra, C.: Transient and permanent fault diagnosis for fpga-based tmr systems. In: Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 1999, pp. 330–338. IEEE Computer Society, Washington, DC (1999)Kim, C.: Detection and location of intermittent faults by monitoring carrier signal channel behavior of electrical interconnection system. In: Electric Ship Technologies Symposium, ESTS 2009, pp. 449–455. IEEE (April 2009

    Daily rhythms of the sleep-wake cycle

    Get PDF
    The amount and timing of sleep and sleep architecture (sleep stages) are determined by several factors, important among which are the environment, circadian rhythms and time awake. Separating the roles played by these factors requires specific protocols, including the constant routine and altered sleep-wake schedules. Results from such protocols have led to the discovery of the factors that determine the amounts and distribution of slow wave and rapid eye movement sleep as well as to the development of models to determine the amount and timing of sleep. One successful model postulates two processes. The first is process S, which is due to sleep pressure (and increases with time awake) and is attributed to a 'sleep homeostat'. Process S reverses during slow wave sleep (when it is called process S'). The second is process C, which shows a daily rhythm that is parallel to the rhythm of core temperature. Processes S and C combine approximately additively to determine the times of sleep onset and waking. The model has proved useful in describing normal sleep in adults. Current work aims to identify the detailed nature of processes S and C. The model can also be applied to circumstances when the sleep-wake cycle is different from the norm in some way. These circumstances include: those who are poor sleepers or short sleepers; the role an individual's chronotype (a measure of how the timing of the individual's preferred sleep-wake cycle compares with the average for a population); and changes in the sleep-wake cycle with age, particularly in adolescence and aging, since individuals tend to prefer to go to sleep later during adolescence and earlier in old age. In all circumstances, the evidence that sleep times and architecture are altered and the possible causes of these changes (including altered S, S' and C processes) are examined

    Tertiary Stratigraphy and Structural Geology, Wellsville Mountains to Junction Hills, North-Central Utah

    Get PDF
    This study integrates detailed mapping of Tertiary deposits along the divide between the lower Bear River basin and the Cache Valley basin with several other techniques to generate a depositional model, define extension-related structures, and compile a geologic history for this part of the northeastern Basin and Range province. The study area is situated along the topographic divide between Box Elder and Cache Counties, Utah, from the Wellsville Mountains north almost to Clarkston Mountain. These ranges are cored by folded and thrusted Paleozoic rocks. They are bound on the west by normal faults of the Wasatch fault zone and on the east by the West Cache fault zone. Between these two fault zones, poorly consolidated Tertiary deposits of the Wasatch Formation and Salt Lake Formation overlie Paleozoic rocks in the foothills and low divide between the north-trending ranges. The Miocene to Pliocene Salt Lake Formation accumulated above non-tuffaceous conglomerates of the Paleocene to Eocene Wasatch Formation, up to 0.5 km thick in the Wellsville Mountains, but thin or absent northward. The Salt Lake Formation in the study area consists of an apparently non-tuffaceous lower conglomerate member, up to 0.5 km thick in the Wellsville Mountains, and a widespread younger tuffaceous and lacustrine member, at least 1 km thick. The traditional names of Collinston Conglomerate and Cache Valley Member were used for these two lithologies. The Cache Valley Member was further subdivided into a local tuffaceous basal conglomerate, a widespread tuffaceous subunit, and an overlying oolitic subunit. Normal faults in the study area comprise three groups. North-striking normal faults are the youngest, and include major range-bounding faults. East-striking normal faults are less numerous, and are cut by the north-striking faults. The southwest-dipping low-to moderate-angle Beaver Dam fault separates the Cache Butte Divide and Junction Hills from the Wellsville Mountains. It may be unique within the area of study, and may comprise a newly identified segment of the Wasatch fault zone. Most of its displacement appears to pre-date the late Miocene, at the time that previous authors have suggested for the onset of Basin-and-Range normal faulting

    Self-testing and self-checking combinational circuits with weakly independent outputs

    No full text
    In this paper we propose a structure dependent method for the systematic design of self--checking error detection circuits wich is well adapted to the technical fault model considered. For online detection, the hardware is in normal operation mode, and for testing in test mode. In the test mode, these error detection circuits guarantee a 100\% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults

    Concurrent Checking of Sequential Circuits by Alternating Inputs

    No full text
    In this paper we investigate how the method of alternating inputs can be applied for concurrent checking of sequential circuits. The state transition function and the output function of the sequential circuit are transformed into corresponding self-dual functions and the memory elements are duplicated. Alternating inputs are submitted to the primary inputs of the sequential circuit. The primary outputs are alternating as long as no error occurs. The error detection probabilities for errors due to single stuck-at faults of the combinational circuits, the memory elements and of the input lines are experimentally determined for benchmark circuits
    corecore